Research Intern - Loop Engineering

About the Company: At SK hynix memory solutions, we're at the forefront of semiconductor innovation, developing advanced memory solutions that power everything from smartphones to data centers. As a global leader in NAND flash technology and memory solutions, we drive the evolution of advancing mobile technology, empowering cloud computing, and pioneering future technologies. Our cutting-edge memory technologies are essential in today's most advanced electronic devices and IT infrastructure, enabling enhanced performance and user experiences across the digital landscape. We're looking for innovative minds to join our mission of shaping the future of technology. At SK hynix memory solutions, you'll be part of a team that's pioneering breakthrough memory solutions while maintaining a strong commitment to sustainability. We're not just adapting to technological change – we're driving it, with significant investments in artificial intelligence, machine learning, and eco-friendly solutions and operational practices. As we continue to expand our market presence and push the boundaries of what's possible in semiconductor technology, we invite you to be part of our journey to creating the next generation of memory solutions that will define the future of computing. Internship Duration: 6 months Hours: 40 hours per week Start Date: Immediately (September/October 2026) Location: San Jose About the role: We are hiring a research intern in loop engineering: best practices for closed-loop flows that automate, optimize, and explore SoC designs. These are AI-assisted hardware/software co-design flows. CHIA, from UC Berkeley, is one example of a framework you may use. You will own a scoped research question with a full-time researcher: build or extend the loop, run the experiments, and write up what the results mean for design automation. What you will do: • Study how a design loop should be structured: which steps belong in it, what feedback each step returns, and how search, verification, and physical-design results drive the next iteration. • Implement the loop with languages and tools such as Chisel and XLS, together with simulation, software build, and physical-design tools. • Apply it to an SoC problem such as microarchitectural exploration, RTL implementation and verification, or power, performance, and area optimization. • Compare loop designs on the quality of the design point, the cost of the search, reproducibility, reuse, and how reliably a failure is diagnosed. • Make the loop reliable enough to rerun: clear interfaces between steps, cached results, regression checks, and reports that support a conclusion. What you bring: • Progress toward a bachelor’s, master’s, or Ph.D. in electrical engineering, computer engineering, computer science, or a related field. • Coursework or project experience in loop engineering, computer architecture, digital design, VLSI, or electronic design automation. • Fluency in Python, and comfort reading and changing an existing codebase. • Ability to pose a small research question, keep a record of what changed, and explain the result. Preferred: • Exposure to RTL (Verilog, SystemVerilog, Chisel, or XLS) or to an SoC design framework. • Experience with an architecture simulator or with RTL simulation. • Familiarity with an AI-assisted hardware/software co-design loop framework, such as CHIA, or with scripted hardware design, verification, or design-space exploration flows. What success looks like: By the end of your internship, you will have a rerunnable co-design loop applied to an SoC problem, a comparison of what worked and what it cost, and a short report on the practice the team should adopt. COMPENSATION: $35/hr - $45/hr